The field effect transistor forms the building block of many modern digital integrated electronic devices. In order to increase the active device density of electronic devices, thin film transistors have been developed which provide adequate transfer characteristics but do not require the use of bulk single-crystal semiconductor material. A thin film field effect transistor may use polycrystalline, amorphous, partially recrystallized, or completely recrystallized semiconductor material comprising its channel. One form of thin film field effect transistor is the bottom gated transistor which comprises a gate conductor formed inwardly from the channel layer. Bottom gated thin film transistors may be used in high density stacked SRAM cells as well as other applications. In these applications, it is desired that the thin film transistors have high drive current and low leakage current.
One of the most important considerations in achieving high drive current with low leakage current is the field enhanced leakage current around the drain region of thin film transistor architectures. During the operation of a thin film field effect transistor device, a large electric field is generated between the drain region and the gate conductor resulting in an unacceptably high leakage current. In order to limit the detrimental effects of this high electric field, transistor architectures have attempted to incorporate spacing between the drain region and the gate conductor to reduce the magnitude of the field between these two regions. These architectures have met with limited success due to the problems of alignment tolerances associated with such architectures.
Accordingly, a need has arisen for a thin film field effect transistor architecture which reduces the field enhanced leakage current associated with the drain of the device but which uses easily controlled processes to provide a high yield architecture.